Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8661179 | Cache memory architecture having reduced tag memory size and method of operation thereof | Alex Rabinovitch, Assaf Rachlevski, Alex Shinkar | 2014-02-25 |
| 7360023 | Method and system for reducing power consumption in a cache memory | — | 2008-04-15 |
| 7020769 | Method and system for processing a loop of instructions | — | 2006-03-28 |
| 5448591 | Method and apparatus for clock and data delivery on a bus | — | 1995-09-05 |
| 5343503 | Method and apparatus for clock and data delivery on a bus | — | 1994-08-30 |
| 5276681 | Process for fair and prioritized access to limited output buffers in a multi-port switch | Fouad A. Tobagi, Joseph M. Gang, Jr. | 1994-01-04 |