Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11977509 | Reconfigurable processor circuit architecture | Paul L. Master, Raymond J. Andraka, Alexei Beliaev, Martin A. Franz, Rene Meessen +1 more | 2024-05-07 |
| 11907157 | Reconfigurable processor circuit architecture | Paul L. Master, Raymond J. Andraka, Alexei Beliaev, Martin A. Franz, Rene Meessen +1 more | 2024-02-20 |
| 11494331 | Reconfigurable processor circuit architecture | Paul L. Master, Raymond J. Andraka, Alexei Beliaev, Martin A. Franz, Rene Meessen +1 more | 2022-11-08 |
| 8863230 | Methods of authenticating a programmable integrated circuit in combination with a non-volatile memory device | James A. Walstrum, Jr., Shalin Umesh Sheth | 2014-10-14 |
| 7987358 | Methods of authenticating a user design in a programmable integrated circuit | James A. Walstrum, Jr., Shalin Umesh Sheth | 2011-07-26 |
| 7768293 | Authentication for information provided to an integrated circuit | — | 2010-08-03 |
| 7535249 | Authentication for information provided to an integrated circuit | — | 2009-05-19 |
| 7454556 | Method to program non-JTAG attached devices or memories using a PLD and its associated JTAG interface | — | 2008-11-18 |
| 7358762 | Parallel interface for configuring programmable devices | James A. Walstrum, Jr., Wayne E. Wennekamp | 2008-04-15 |
| 7281082 | Flexible scheme for configuring programmable semiconductor devices using or loading programs from SPI-based serial flash memories that support multiple SPI flash vendors and device families | — | 2007-10-09 |
| 7243227 | Method and apparatus to copy protect software programs | — | 2007-07-10 |
| 6691266 | Bus mastering debugging system for integrated circuits | Steven Winegarden, Arye Ziklik | 2004-02-10 |
| 5737234 | Method of optimizing resource allocation starting from a high level block diagram | Jorge P. Seidel | 1998-04-07 |
| 5617573 | State splitting for level reduction | Alan Y. Huang, Sanjeev Kwatra | 1997-04-01 |
| 5574655 | Method of allocating logic using general function components | Jorge P. Seidel | 1996-11-12 |
| 5553001 | Method for optimizing resource allocation starting from a high level | Jorge P. Seidel | 1996-09-03 |
| 5499192 | Method for generating logic modules from a high level block diagram | Jorge P. Seidel, Steven Hennick Kelem | 1996-03-12 |
| 5422833 | Method and system for propagating data type for circuit design from a high level block diagram | Steven Hennick Kelem | 1995-06-06 |