Issued Patents All Time
Showing 26–49 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7012985 | Frequency division of an oscillating signal involving a divisor fraction | — | 2006-03-14 |
| 6927608 | Low power low voltage differential signaling driver | Mingdeng Chen | 2005-08-09 |
| 6819156 | High-speed differential flip-flop | — | 2004-11-16 |
| 6784822 | Method and circuit for folded analog-to-digital converter (ADC) using frequency detectors and time detectors | Ahmed Younis | 2004-08-31 |
| 6677879 | Method and circuit for folded analog-to-digital converter (ADC) using frequency detectors and time detectors | Ahmed Younis | 2004-01-13 |
| 6621307 | Method and circuit for determining frequency and time variations between electronic signals | Ahmed Younis | 2003-09-16 |
| 6617887 | Differential comparator with offset correction | — | 2003-09-09 |
| 6611218 | Transmitter with multiphase data combiner for parallel to serial data conversion | Jinghui Lu | 2003-08-26 |
| 6586964 | Differential termination with calibration for differential signaling | Michael Ren Kent | 2003-07-01 |
| 6553443 | Method and apparatus for prioritizing interrupts in a communication system | Imran Baqai, Jeffrey J. Anderson | 2003-04-22 |
| 6535030 | Differential comparator with offset correction | — | 2003-03-18 |
| 6501339 | Ring oscillators with improved signal-path matching for high-speed data communications | Ahmed Younis, Moises E. Robinson, Brian Brunn | 2002-12-31 |
| 5764581 | Dynamic ram with two-transistor cell | — | 1998-06-09 |
| 5638440 | Protection circuit for telephone systems | Walter S. Schopfer, Sergio R. Ramirez | 1997-06-10 |
| 5420815 | Digital multiplication and accumulation system | John G. Bartkowiak | 1995-05-30 |
| 5347480 | Digital signal processing apparatus | Safdar M. Asghar, John G. Bartkowiak | 1994-09-13 |
| 5299144 | Architecture for covariance matrix generation | John G. Bartkowiak | 1994-03-29 |
| 5282153 | Arithmetic logic unit | John G. Bartkowiak | 1994-01-25 |
| 5272654 | System for converting a floating point signed magnitude binary number to a two's complement binary number | — | 1993-12-21 |
| 5020025 | Capacitively coupled read-only memory | Clayton D. English | 1991-05-28 |
| 4926363 | Modular test structure for single chip digital exchange controller | — | 1990-05-15 |
| 4918332 | TTL output driver gate configuration | — | 1990-04-17 |
| 4897810 | Asynchronous interrupt status bit circuit | — | 1990-01-30 |
| 4862409 | Asynchronous interrupt status bit circuit | — | 1989-08-29 |