Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9377996 | Parameterized digital divider | — | 2016-06-28 |
| 8664984 | Pulse synchronizer circuit | — | 2014-03-04 |
| 7755397 | Methods and apparatus for digital phase detection with improved frequency locking | — | 2010-07-13 |
| 7685454 | Signal buffering and retiming circuit for multiple memories | William P. Cornelius, Stephen A. Masnica, Parag Parikh, Anthony W. Seaman | 2010-03-23 |
| 7342983 | Apparatus and method for digitally filtering spurious transitions on a digital signal | — | 2008-03-11 |
| 7231467 | Method and apparatus for providing an inter integrated circuit interface with an expanded address range and efficient priority-based data throughput | Thomas E. Baker, Laurence E. Bays | 2007-06-12 |
| 7157932 | Adjusting settings of an I/O circuit for process, voltage, and/or temperature variations | Anthony W. Seaman, Stefan A. Siegel | 2007-01-02 |
| 7032120 | Method and apparatus for minimizing power requirements in a computer peripheral device while in suspend state and returning to full operation state without loss of data | Richard J. Niescier | 2006-04-18 |
| 6999581 | Event detection circuit | Keith Eugene Hollenbach, Donald R. Laturell, Steven B. Witmer | 2006-02-14 |
| 6873650 | Transmission rate compensation for a digital multi-tone transceiver | Raja Banerjea, Bahman Barazesh, Kannan Rajamani | 2005-03-29 |
| 6753709 | Digital clock rate multiplier method and apparatus | — | 2004-06-22 |
| 6744888 | Line interface circuit with event detection signaling | Keith Eugene Hollenbach, Donald R. Laturell, Steven B. Witmer | 2004-06-01 |
| 6427216 | Integrated circuit testing using a high speed data interface bus | Jeffrey P. Grundvig | 2002-07-30 |
| 6404780 | Synchronizing data transfer protocol across high voltage interface | Donald R. Laturell, Lane A. Smith | 2002-06-11 |
| 6327649 | Apparatus for developing internal ROM code using a ROM bus external interface | — | 2001-12-04 |
| 6278302 | Digital power-up reset circuit | — | 2001-08-21 |
| 6278307 | Method and apparatus for 50% duty-cycle programmable divided-down clock with even and odd divisor rates | — | 2001-08-21 |
| 6184807 | Glitch-free bi-phased encoder | Dennis A. Brooks, Richard Muscavage | 2001-02-06 |