Issued Patents All Time
Showing 26–45 of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6506641 | Use of selective oxidation to improve LDMOS power transistors | Charles Walter Pearce | 2003-01-14 |
| 6372600 | Etch stops and alignment marks for bonded wafers | John Desko | 2002-04-16 |
| 6303961 | Complementary semiconductor devices | — | 2001-10-16 |
| 6228750 | Method of doping a semiconductor surface | — | 2001-05-08 |
| 6140170 | Manufacture of complementary MOS and bipolar integrated circuits | — | 2000-10-31 |
| 6013934 | Semiconductor structure for thermal shutdown protection | Milton L. Embree | 2000-01-11 |
| 5959342 | Semiconductor device having a high voltage termination improvement | — | 1999-09-28 |
| 5949128 | Bipolar transistor with MOS-controlled protection for reverse-biased emitter-base junction | — | 1999-09-07 |
| 5894154 | P-channel MOS transistor | — | 1999-04-13 |
| 5773338 | Bipolar transistor with MOS-controlled protection for reverse-biased emitter-based junction | — | 1998-06-30 |
| 5728607 | Method of making a P-channel bipolar transistor | — | 1998-03-17 |
| 5670396 | Method of forming a DMOS-controlled lateral bipolar transistor | — | 1997-09-23 |
| 5557125 | Dielectrically isolated semiconductor devices having improved characteristics | — | 1996-09-17 |
| 5541429 | High voltage semiconductor device having improved electrical ruggedness and reduced cell pitch | — | 1996-07-30 |
| 5534721 | Area-efficient layout for high voltage lateral devices | — | 1996-07-09 |
| 5420457 | Lateral high-voltage PNP transistor | — | 1995-05-30 |
| 5395776 | Method of making a rugged DMOS device | — | 1995-03-07 |
| 5381031 | Semiconductor device with reduced high voltage termination area and high breakdown voltage | — | 1995-01-10 |
| 5360987 | Semiconductor photodiode device with isolation region | — | 1994-11-01 |
| 4573065 | Radial high voltage switch structure | Hans W. Becke, John Gammel, Adrian R. Hartman, Robert K. Smith | 1986-02-25 |