Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6912560 | Adder with improved overflow flag generation | — | 2005-06-28 |
| 6819971 | Fast computation of overflow flag in a bit manipulation unit | Mazhar M. Alidina | 2004-11-16 |
| 6640324 | Boundary scan chain routing | — | 2003-10-28 |
| 6584484 | Incorporation of split-adder logic within a carry-skip adder without additional propagation delay | Bimal Patel | 2003-06-24 |
| 6539413 | Prefix tree adder with efficient sum generation | Hosahalli R. Srinivas | 2003-03-25 |
| 6529931 | Prefix tree adder with efficient carry generation | Matthew Besz, Ravi Kolagotla, Christopher John Nicol | 2003-03-04 |
| 6173304 | Joint optimization of modified-booth encoder and partial product generator | Ravi Kolagotla | 2001-01-09 |
| 6122655 | Efficient use of inverting cells in multiplier converter | Ravi Kolagotla | 2000-09-19 |