Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12039413 | Cognitive modeling apparatus including multiple knowledge node and supervisory node devices | Michael E. Cormier, Earl D. Cox, William E. Thackrey, Joseph McGlynn | 2024-07-16 |
| 11348016 | Cognitive modeling apparatus for assessing values qualitatively across a multiple dimension terrain | Michael E. Cormier, Earl D. Cox, William E. Thackrey, Joseph McGlynn | 2022-05-31 |
| 11238350 | Cognitive modeling system | Michael E. Cormier, Earl D. Cox, William E. Thackrey, Joseph McGlynn | 2022-02-01 |
| 11017298 | Cognitive modeling apparatus for detecting and adjusting qualitative contexts across multiple dimensions for multiple actors | Michael E. Cormier, Earl D. Cox, William E. Thackrey, Joseph McGlynn | 2021-05-25 |
| 8854076 | Single event transient direct measurement methodology and circuit | Radu Dumitru | 2014-10-07 |
| 8222916 | Single event transient direct measurement methodology and circuit | Radu Dumitru | 2012-07-17 |
| 7737535 | Total ionizing dose suppression transistor architecture | — | 2010-06-15 |
| 7656699 | Radiation-hardened programmable device | David B. Kerwin | 2010-02-02 |
| 7518218 | Total ionizing dose suppression transistor architecture | — | 2009-04-14 |
| 7251150 | Radiation-hardened programmable device | David B. Kerwin | 2007-07-31 |
| 7071749 | Error correcting latch | — | 2006-07-04 |
| 6917533 | Radiation-hardened programmable device | David B. Kerwin | 2005-07-12 |
| 6831496 | Error correcting latch | — | 2004-12-14 |
| 6573774 | Error correcting latch | — | 2003-06-03 |
| 6570234 | Radiation resistant integrated circuit design | — | 2003-05-27 |
| 6453447 | Method for fabricating integrated circuits | Debra S. Harris, Michael D. Lahey, Stacia L. Patton, Peter M. Pohlenz | 2002-09-17 |
| 6414360 | Method of programmability and an architecture for cold sparing of CMOS arrays | — | 2002-07-02 |
| 6346427 | Parameter adjustment in a MOS integrated circuit | Debra S. Harris, Michael D. Lahey, Stacia L. Patton, Peter M. Pohlenz | 2002-02-12 |
| 5870332 | High reliability logic circuit for radiation environment | Michael D. Lahey, Debra S. Harris, Michael J. Barry | 1999-02-09 |
| 5543736 | Gate array architecture and layout for deep space applications | Charles R. Gregory, Douglas W. Garvie | 1996-08-06 |
| 4344091 | Random access memory imaging system | John P. Petty | 1982-08-10 |
| 4275380 | Topography for integrated circuits pattern recognition array | Wayne R. Gravelle | 1981-06-23 |