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Cognitive modeling apparatus including multiple knowledge node and supervisory node devices |
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Cognitive modeling apparatus for detecting and adjusting qualitative contexts across multiple dimensions for multiple actors |
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Single event transient direct measurement methodology and circuit |
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2014-10-07 |
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Single event transient direct measurement methodology and circuit |
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Total ionizing dose suppression transistor architecture |
— |
2010-06-15 |
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Radiation-hardened programmable device |
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2010-02-02 |
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Total ionizing dose suppression transistor architecture |
— |
2009-04-14 |
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Error correcting latch |
— |
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Radiation-hardened programmable device |
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2005-07-12 |
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Error correcting latch |
— |
2004-12-14 |
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Error correcting latch |
— |
2003-06-03 |
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— |
2003-05-27 |
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Method for fabricating integrated circuits |
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Method of programmability and an architecture for cold sparing of CMOS arrays |
— |
2002-07-02 |
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High reliability logic circuit for radiation environment |
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1999-02-09 |
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Gate array architecture and layout for deep space applications |
Charles R. Gregory, Douglas W. Garvie |
1996-08-06 |
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Random access memory imaging system |
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1982-08-10 |
| 4275380 |
Topography for integrated circuits pattern recognition array |
Wayne R. Gravelle |
1981-06-23 |
