Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12332683 | Synchronous reset deassertion circuit | Sarma Jonnavithula, Mohan Krishna Vedam, Christopher LaFrieda, Virantha Ekanayake | 2025-06-17 |
| 11681324 | Synchronous reset deassertion circuit | Sarma Jonnavithula, Mohan Krishna Vedam, Christopher LaFrieda, Virantha Ekanayake | 2023-06-20 |
| 10831959 | Embedded FPGA timing sign-off | Shirish Jawale | 2020-11-10 |