Issued Patents 2025
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411694 | Processor having adaptive pipeline with latency reduction logic that selectively executes instructions to reduce latency | Shrey Bhatia, Jeroen Vliegen | 2025-09-09 |
| 12353308 | Processor with debug pipeline | Shrey Bhatia, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch | 2025-07-08 |