Issued Patents 2025
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12433003 | 2D-channel transistor structure with asymmetric substrate contacts | Cheng-Ting Chung, Chien-Hong Chen, Mahaveer Sathaiya Dhanyakumar, Hou-Yu Chen, Kuan-Lun Cheng | 2025-09-30 |
| 12424298 | Control circuit, memory system and control method | Win-San Khwa, Jen-Chieh Liu, Meng-Fan Chang, Tung Ying Lee | 2025-09-23 |
| 12419103 | Dielectric walls for complementary field effect transistors | Cheng-Ting Chung, Yi-Bo Liao | 2025-09-16 |
| 12405736 | Operating methods, memory controllers, and memory systems | Xianwu Luo | 2025-09-02 |
| 12408387 | Transistor with a negative capacitance and a method of creating the same | Feng Yuan, Ming-Shiang Lin, Chia-Cheng Ho, Tzu-Chung Wang, Tung Ying Lee | 2025-09-02 |
| 12394706 | Device with gate-to-drain via and related methods | Yi-Bo Liao | 2025-08-19 |
| 12396235 | Semiconductor device and method for forming the same | Mahaveer Sathaiya Dhanyakumar, Cheng-Ting Chung, Chien-Hong Chen, Chung-Wei Wu | 2025-08-19 |
| 12376322 | Semiconductor device having thin bottom channel and manufacturing method thereof | Wang-Chun Huang, Hou-Yu Chen, Chih-Hao Wang | 2025-07-29 |
| 12349409 | Semiconductor device having a gate contact on a low-k liner | Meng-Huan Jao, Huan-Chieh Su, Yi-Bo Liao, Cheng-Chi Chuang, Chih-Hao Wang | 2025-07-01 |
| 12349421 | 2D channel with self-aligned source/drain | Cheng-Ting Chung | 2025-07-01 |
| 12336216 | Ferroelectric semiconductor device and method | Chia-Cheng Ho, Ming-Shiang Lin | 2025-06-17 |
| 12236100 | Operating method, memory controller, and memory system | Xianwu Luo | 2025-02-25 |
| 12191371 | Field effect transistor with disabled channels and method | Yu-Xuan Huang, Hou-Yu Chen, Zhi-Chang Lin, Chih-Hao Wang | 2025-01-07 |