Issued Patents 2025
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12412605 | Bit line pre-charge circuit and method | Che-Ju Yeh, Yu-Hao Hsu, Cheng Hung Lee | 2025-09-09 |
| 12400708 | Memory device and method for reducing active power consumption thereof using address control | Chien-Yuan Chen, Cheng Hung Lee | 2025-08-26 |
| 12400723 | Latch type sense amplifier for testing | Hua-Hsin Yu, Cheng Hung Lee, Hung-Jen Liao | 2025-08-26 |
| 12354647 | Memory device sense amplifier control | Chien-Yuan Chen, Cheng Hung Lee | 2025-07-08 |
| 12347483 | Arrangements of memory devices and methods of operating the memory devices | Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao | 2025-07-01 |
| 12322438 | Latch circuit formed by modified memory cells | Hua-Hsin Yu, Cheng Hung Lee, Hung-Jen Liao | 2025-06-03 |
| 12300605 | Reducing internal node loading in combination circuits | Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao, Kao-Cheng Lin, Wei Min Chan | 2025-05-13 |
| 12254919 | Sub-word line driver placement for memory device | Yi-Tzu Chen, Ching-Wei Wu, Hung-Jen Liao | 2025-03-18 |
| 12249391 | Latch type sense amplifier | Hua-Hsin Yu, Hung-Jen Liao, Cheng Hung Lee | 2025-03-11 |
| 12230632 | Integrated circuit layout and method thereof | Chien-Yuan Chen | 2025-02-18 |
| 12205664 | Memory circuit and method of operating same | Hua-Hsin Yu, Cheng Hung Lee, Hung-Jen Liao | 2025-01-21 |