Issued Patents 2025
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12353503 | Output array neuron conversion and calibration for analog neural memory in deep learning artificial neural network | Hieu Van Tran, Stephen Trinh, Thuan Vu, Stanley Hong, Mark Reiten +1 more | 2025-07-08 |
| 12354651 | Neural network classifier using array of three-gate non-volatile memory cells | Hieu Van Tran, Steven Lemke, Nhan Do, Mark Reiten | 2025-07-08 |
| 12347484 | Memory device of non-volatile memory cells | Hieu Van Tran, Nhan Do, Farnood Merrikh Bayat, Xinjie Guo, Dmitri Strukov +1 more | 2025-07-01 |
| 12300313 | Deep learning neural network classifier using non-volatile memory array | Farnood Merrikh Bayat, Xinjie Guo, Dmitri Strukov, Nhan Do, Hieu Van Tran +1 more | 2025-05-13 |
| 12299562 | Analog neural memory array in artificial neural network with source line pulldown mechanism | Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Han Tran +1 more | 2025-05-13 |
| 12283314 | Neural network classifier using array of three-gate non-volatile memory cells | Hieu Van Tran, Steven Lemke, Nhan Do, Mark Reiten | 2025-04-22 |
| 12249368 | Neural network classifier using array of three-gate non-volatile memory cells | Hieu Van Tran, Steven Lemke, Nhan Do, Mark Reiten | 2025-03-11 |
| 12205655 | Testing of analog neural memory cells in an artificial neural network | Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly +3 more | 2025-01-21 |
| 12198043 | Output circuit | Hieu Van Tran, Mark Reiten, Nhan Do | 2025-01-14 |
| 12200926 | Input function circuit block and output neuron circuit block coupled to a vector-by-matrix multiplication array in an artificial neural network | Hieu Van Tran, Steven Lemke, Nhan Do, Mark Reiten | 2025-01-14 |