Issued Patents 2025
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431182 | Row hammer mitigation | Torsten Partsch | 2025-09-30 |
| 12399636 | Multi-modal refresh of dynamic, random-access memory | Steven C. Woo, Michael Raymond Miller | 2025-08-26 |
| 12379858 | Memory module with persistent calibration | Brent Haukness | 2025-08-05 |
| 12375109 | Integration of compression algorithms with error correction codes | Michael Alexander Hamburg, John Eric Linstadt, Evan Lawrence Erickson | 2025-07-29 |
| 12367921 | System application of DRAM component with cache mode | Frederick A. Ware, Michael Raymond Miller, Collins Williams | 2025-07-22 |
| 12353337 | Methods and circuits for aggregating processing units and dynamically allocating memory | Steven C. Woo | 2025-07-08 |
| 12346604 | Stacked device communication | Michael Raymond Miller, Steven C. Woo | 2025-07-01 |
| 12347480 | Memory system with multiple open rows per bank | John Eric Linstadt, Liji Gopalakrishnan | 2025-07-01 |
| 12346567 | Partial array refresh timing | Liji Gopalakrishnan, John Eric Linstadt | 2025-07-01 |
| 12327049 | Stacked memory device with paired channels | — | 2025-06-10 |
| 12292601 | Bus distribution using multiwavelength multiplexing | Mark D. Kellam, Dongyun Lee, Steven C. Woo | 2025-05-06 |
| 12230355 | Hierarchical bank group timing | John Eric Linstadt, Liji Gopalakrishnan | 2025-02-18 |
| 12223207 | Memory component having internal read-modify-write operation | Frederick A. Ware | 2025-02-11 |
| 12217784 | Boosted writeback voltage | Brent Haukness | 2025-02-04 |
| 12190974 | DRAM retention test method for dynamic error correction | Ely Tsern, Frederick A. Ware, Suresh Rajan | 2025-01-07 |
| 12190990 | Deferred fractional memory row activation | James E. Harris, Frederick A. Ware, Ian Shaeffer | 2025-01-07 |