Issued Patents 2025
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12394714 | Semiconductor device including dielectric insert structure directly under buried word line and method for forming the same | Janbo Zhang | 2025-08-19 |
| 12396152 | Semiconductor structure and method for forming the same | Yi-Wang Jhan, Fu-Che Lee, Gang-Yi Lin, An-Chi Liu, Yifei Yan | 2025-08-19 |
| 12389617 | Semiconductor device and method of fabricating the same | Janbo Zhang | 2025-08-12 |
| 12381082 | Semiconductor structure, method for fabricating thereof, and method for fabricating semiconductor layout | Gang-Yi Lin, Yi-Wang Jhan, Yifei Yan, Xiaopei Fang | 2025-08-05 |
| 12374621 | Semiconductor structure and method of manufacturing the same | Janbo Zhang | 2025-07-29 |
| 12363885 | Semiconductor memory device and method of fabricating the same | Janbo Zhang | 2025-07-15 |
| 12342536 | Semiconductor memory device having buried word line with a neck profile portion | Janbo Zhang | 2025-06-24 |
| 12334345 | Dynamic random access memory device with active regions of different profile roughness and method for forming the same | Yaoguang Xu, Hsien-Shih Chu, Yun-Fan Chou, Chaoxiong Wang | 2025-06-17 |
| 12272594 | Semiconductor device and method of fabricating the same having a second active region disposed at an outer side of a first active region | Janbo Zhang | 2025-04-08 |
| 12261136 | Semiconductor structure | Yi-Wang Jhan, Yung-Tai Huang, Xin You, Xiaopei Fang | 2025-03-25 |
| 12256533 | Semiconductor memory device and method of fabricating the same | Ken-Li Chen, Yifei Yan | 2025-03-18 |
| 12237369 | Semiconductor device with shallow trench isolation having multi-stacked layers and method of forming the same | Huixian Lai, Chao-Wei Lin, Chiayi Chu | 2025-02-25 |
| 12225715 | Semiconductor device having semiconductor layers disposed between upper portions of the isolation structures and the active regions | Janbo Zhang | 2025-02-11 |
| 12224283 | Semiconductor memory device | Janbo Zhang | 2025-02-11 |
| 12200923 | Method of fabricating semiconductor device having bit line comprising a plurality of pins extending toward the substrate | Janbo Zhang, Li-Wei Feng | 2025-01-14 |