Issued Patents 2025
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423252 | Systems and methods for reducing latency and improving performance in a peripheral component interconnect express (PCIe) system | Madhu Yashwanth Boenapalli, Vinod Kumar Kuruma, Sai Praneeth Sreeram, Ravindranath DODDI | 2025-09-23 |
| 12417196 | Systems and methods for reducing latency and power consumption in a peripheral component interconnect express (PCIe) system | Madhu Yashwanth Boenapalli, Ravindranath DODDI, Vinod Kumar Kuruma, Sai Praneeth Sreeram | 2025-09-16 |
| 12346592 | Write throughput improvement of flash memory device | Madhu Yashwanth Boenapalli, Sai Praneeth Sreeram | 2025-07-01 |
| 12333146 | Packed commands for communicating with flash memory system | Madhu Yashwanth Boenapalli, Sai Praneeth Sreeram | 2025-06-17 |
| 12326828 | Systems and methods for performing link speed switching in a peripheral component interconnect express (PCIe) system | Madhu Yashwanth Boenapalli, Kaustub Naidu Paila Ram, Sravani Devineni, Sai Praneeth Sreeram, Vinod Kumar Kuruma +1 more | 2025-06-10 |
| 12298912 | Enhanced write buffer flush scheme for memory devices with high density storage memory architecture | Rajesh Biswal, Manmeet AHLUWALIA, Madhu Yashwanth Boenapalli, Sai Praneeth Sreeram | 2025-05-13 |
| 12197771 | Universal flash storage read throughput enhancements | Sravani Devineni, Sai Praneeth Sreeram, Madhu Yashwanth Boenapalli | 2025-01-14 |
| 12197775 | Memory devices write buffer management | Santhosh Reddy AKAVARAM, Sonali Jabreva, Prakhar Srivastava, Yogananda Rao Chillariga, Madhu Yashwanth Boenapalli | 2025-01-14 |