Issued Patents 2025
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12432545 | Controlling switch timing in time division duplexing devices | Priyangshu Ghosh, Raveesh Juneja | 2025-09-30 |
| 12413530 | Data processing system with link-based resource allocation for reconfigurable processors | Raghunath Shenbagam | 2025-09-09 |
| 12402089 | Techniques for performing tracking using a physical broadcast channel | Swarupa Gandhi Vudata, Vishnu Namboodiri Karakkad Kesavan Namboodiri, Mahendran Kamatchi, Shivaprasad Boora | 2025-08-26 |
| 12380041 | Method and apparatus for data transfer between accessible memories of multiple processors in a heterogeneous processing system using two memory to memory transfer operations | Arnav GOEL, Neal SANGHVI, Jiayu Bai, Qi ZHENG | 2025-08-05 |
| 12362871 | Physical broadcast channel for channel correction | Yuhung Kao | 2025-07-15 |
| 12346729 | Runtime virtualization of reconfigurable data flow resources | Conrad Alexander TURLIK, Arnav GOEL, Qi ZHENG, Raghunath Shenbagam, Anand Misra +2 more | 2025-07-01 |
| 12340195 | Handling interrupts from a virtual function in a system with a reconfigurable processor | Manish K. Shah, Paul J. Jordan, Maran WILSON | 2025-06-24 |
| 12298932 | Load balancing system for the execution of applications on reconfigurable processors | Milad Sharif, Qi ZHENG, Neal SANGHVI, Jiayu Bai, Arnav GOEL | 2025-05-13 |
| 12261623 | Decoding metadata encoded in error correction codes | Srikanth Dakshinamoorthy, Majid Anaraki Nemati, Perry Willmann Remaklus, Jr. | 2025-03-25 |
| 12242403 | Direct access to reconfigurable processor memory | Conrad Alexander TURLIK, Sudhakar Dindukurti, Anand Misra, Arjun SABNIS, Milad Sharif +3 more | 2025-03-04 |
| 12229057 | Method and apparatus for selecting data access method in a heterogeneous processing system with multiple processors | Arnav GOEL, Neal SANGHVI, Jiayu Bai, Qi ZHENG | 2025-02-18 |
| 12210468 | Data transfer between accessible memories of multiple processors incorporated in coarse-grained reconfigurable (CGR) architecture within heterogeneous processing system using one memory to memory transfer operation | Arnav GOEL, Neal SANGHVI, Jiayu Bai, Qi ZHENG | 2025-01-28 |