Issued Patents 2025
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12314130 | Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilization | Massimo Sutera, Sandeep Brahmadathan | 2025-05-27 |
| 12282064 | Component die validation built-in self-test (VBIST) engine | Sandeep Brahmadathan, Jared Eric Bendt, Kedar KARANDIKAR, Stephan Jourdan | 2025-04-22 |
| 12204410 | Integrated error correction code (ECC) and parity protection in memory control circuits for increased memory utilization | Massimo Sutera, Sandeep Brahmadathan | 2025-01-21 |