Issued Patents 2025
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430108 | Multistage compiler architecture | Ulf Hanebutte, Senad Durakovic, Fu-Hwa Wang, Mohana Tandyala | 2025-09-30 |
| 12293174 | Method and system for memory management within machine learning inference engine | Nikhil Bernard John Stephen, Senad Durakovic, Pranav Jonnalagadda, Ulf Hanebutte | 2025-05-06 |
| 12190086 | Method and apparatus for ML graphs by a compiler | Ulf Hanebutte, Senad Durakovic, Pranav Jonnalagadda | 2025-01-07 |