Issued Patents 2025
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423058 | Systolic array with input reduction to multiple reduced inputs | Paul Gilbert Meyer, Thomas A. Volpe, Ron Diamant, Nishith Desai, Thomas Elmer | 2025-09-23 |
| 12333274 | Data-type-aware clock-gating | Thomas A. Volpe, Sundeep Amirineni, Nishith Desai, Ron Diamant | 2025-06-17 |