Issued Patents 2025
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12361990 | Memory with external clock synchronized operation | Sanjiv Kainth, Anurag Garg | 2025-07-15 |
| 12340864 | Interface level-shifter dual-rail memory architecture | Shishir Kumar, Anurag Garg, Peter Lee, John E. Barth, Jr. | 2025-06-24 |
| 12340865 | Reduced circuit area memory device with a half-word memory architecture | Niranjan Behera | 2025-06-24 |
| 12308091 | Pseudo-2-port memory with dual pre-charge circuits | Michael Lee, Vijit Gadi | 2025-05-20 |
| 12243581 | Output driver level-shifting latch circuit for dual-rail memory | — | 2025-03-04 |