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CS Cadence Design Systems: 2 patents #9 of 106Top 9%
📍 Noida, IN: #10 of 140 inventorsTop 8%
Overall (2025): #122,976 of 469,880Top 30%
2
Patents 2025

Issued Patents 2025

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
12218786 Clock recovery for PAM4 signaling using bin-map Rohit Mishra, Harshit Jaiswal, Shubham Agarwal 2025-02-04
12199770 High accuracy timestamping of transmissions at physical layer of communication devices and systems Shubham Agarwal, Harshdeep Verma, Rohit Mishra 2025-01-14