Issued Patents 2025
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430268 | Efficient signaling scheme for high-speed ultra short reach interfaces | Paul Langner | 2025-09-30 |
| 12341569 | Wireline link with crosstalk reduction based on controlled channel delay | Ali Khoshniat | 2025-06-24 |
| 12314567 | Multi-chip module (MCM) with multi-port unified memory | Syrus Ziai | 2025-05-27 |
| 12248679 | Multi-chip module (MCM) with multi-port unified memory | Syrus Ziai | 2025-03-11 |
| 12248413 | Universal memory interface utilizing die-to-die (D2D) interfaces between chiplets | Syrus Ziai, Curtis R. McAllister | 2025-03-11 |
| 12248418 | Efficient signaling scheme for high-speed ultra short reach interfaces | Paul Langner | 2025-03-11 |
| 12248419 | Interface conversion circuitry for universal chiplet interconnect express (UCIe) | Kevin S. Donnelly | 2025-03-11 |
| 12248421 | Chiplet gearbox for low-cost multi-chip module applications | — | 2025-03-11 |
| 12204482 | Memory chiplet with efficient mapping of memory-centric interface to die-to-die (D2D) unit interface modules | Kevin S. Donnelly | 2025-01-21 |
| 12204759 | Multi-chip module (MCM) with multi-port unified memory | Syrus Ziai | 2025-01-21 |
| 12204840 | Multi-chip module (MCM) with multi-port unified memory | — | 2025-01-21 |
| 12190038 | Multi-chip module (MCM) with multi-port unified memory | — | 2025-01-07 |