Issued Patents 2024
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12165739 | Systems and methods for controlling power management operations in a memory device | Sanjeev Kumar Jain, Sahil Preet Singh | 2024-12-10 |
| 12136454 | Memory device having a comparator circuit | Jaspal Singh Shah | 2024-11-05 |
| 12131770 | Word line booster circuit and method | — | 2024-10-29 |
| 12073877 | Robust circuit for negative bit line generation in SRAM cells | Sanjeev Kumar Jain | 2024-08-27 |
| 12033719 | Semiconductor device and method of operating the same | Shiba Mohanty | 2024-07-09 |
| 12009055 | Far end driver for memory clock | — | 2024-06-11 |
| 11935589 | Bit line pre-charge circuit for power management modes in multi bank SRAM | Sanjeev Kumar Jain, Ruchin Jain, Arun Achyuthan | 2024-03-19 |
| 11929113 | Variable voltage bit line precharge | Adrian Earle | 2024-03-12 |
| 11929110 | Memory circuit and method of operating same | Sanjeev Kumar Jain, Ishan Khera | 2024-03-12 |
| 11922998 | Memory device with global and local latches | Sahil Preet Singh | 2024-03-05 |
| 11894086 | Method, device, and circuit for high-speed memories | Jaspal Singh Shah | 2024-02-06 |