WP

Wladimir Plagges

SY Synopsys: 1 patents #48 of 291Top 20%
📍 Santiago, CL: #8 of 91 inventorsTop 9%
Overall (2024): #192,096 of 561,600Top 35%
1
Patents 2024

Issued Patents 2024

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
12158770 Power-efficient enable signal for fanin-based sequential clock gating on enabled flip flops Muzaffer Hiraoglu, Esteban Osses 2024-12-03