Issued Patents 2024
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12182413 | Area-optimized row hammer mitigation | Sujeet Ayyapureddi, Yang Lu, Edmund J. Gieske, Cagdas Dirik, Ameen D. Akel +3 more | 2024-12-31 |
| 12153832 | Memory searching component | Elliott C. Cooper-Balis, Paul Rosenfeld | 2024-11-26 |
| 12153796 | Non-deterministic memory protocol | James A. Hall, Jr., Frank F. Ross | 2024-11-26 |
| 12124741 | Memory module interfaces | — | 2024-10-22 |
| 12112786 | Command scheduling component for memory | Patrick A. La Fratta, Jeffrey L. Scott, Laurent Isenegger | 2024-10-08 |
| 12093565 | Memory protocol | Frank F. Ross | 2024-09-17 |
| 12067270 | Memory device security and row hammer mitigation | Yang Lu, Sujeet Ayyapureddi, Edmund J. Gieske, Cagdas Dirik, Ameen D. Akel +3 more | 2024-08-20 |
| 12056375 | Port arbitration | Patrick A. La Fratta, Shashank Adavally, Jeffrey L. Scott | 2024-08-06 |
| 11972152 | Memory sub-system for supporting deterministic and non-deterministic commands based on command expiration and the state of the intermediate command queue | Patrick A. La Fratta | 2024-04-30 |
| 11947796 | Memory protocol | James A. Hall, Jr. | 2024-04-02 |
| 11928055 | Memory sub-system for decoding non-power-of-two addressable unit address boundaries | Patrick A. La Fratta, Chandrasekhar Nagarajan | 2024-03-12 |
| 11914530 | Memory having internal processors and data communication methods in memory | Dan Skinner, Todd A. Merritt, J. Thomas Pawlowski | 2024-02-27 |
| 11899591 | Dynamically sized redundant write buffer with sector-based tracking | Cagdas Dirik | 2024-02-13 |
| 11893279 | Access tracking in memory | Cagdas Dirik, Elliott C. Cooper-Balis | 2024-02-06 |
| 11886348 | Interleaved cache prefetching | Laurent Isenegger, Cagdas Dirik | 2024-01-30 |