Issued Patents 2024
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12176031 | Divided clock transmission in a three-dimensional stacked memory device | Vijayakrishna J. Vankayala, Jason M. Brown | 2024-12-24 |
| 12051463 | Decoder architecture for memory device | Ferdinando Bedeschi, Jeffrey E. Koelling, Riccardo Muzzetto, Corrado Villa | 2024-07-30 |
| 12020743 | Memory device architecture using multiple physical cells per bit to improve read margin and to alleviate the need for managing demarcation read voltages | Joseph M. McCrate, Robert J. Gleixner, Ramin Ghodsi | 2024-06-25 |
| 12014765 | Intra-package memory die communication structures | — | 2024-06-18 |
| 12008236 | Tuned datapath in stacked memory device | Bret Johnson | 2024-06-11 |
| 11972147 | Memory die stack chip id-based command structure | — | 2024-04-30 |
| 11967373 | Pre-decoder circuitry | Vijayakrishna J. Vankayala, Jeffrey E. Koelling, Mingdong Cui, Ramachandra Rao Jogu | 2024-04-23 |
| 11960744 | Register operation in memory devices | — | 2024-04-16 |
| 11923002 | Varying-polarity read operations for polarity-written memory cells | Innocenzo Tortorelli, Fabio Pellizzer | 2024-03-05 |
| 11900999 | Memory cycling tracking for threshold voltage variation systems and methods | — | 2024-02-13 |
| 11887665 | Memory cell programming that cancels threshold voltage drift | — | 2024-01-30 |