Issued Patents 2024
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12135987 | Thread scheduling control and memory splitting in a barrel processor | Chris Baronne, John Amelio | 2024-11-05 |
| 12111770 | Silent cache line eviction | Tony M. Brewer | 2024-10-08 |
| 12111758 | Synchronized request handling at a memory device | Tony M. Brewer | 2024-10-08 |
| 12079516 | Host-preferred memory operation | Tony M. Brewer | 2024-09-03 |
| 12020064 | Rescheduling a failed memory request in a processor | Chris Baronne, John Amelio | 2024-06-25 |
| 12013788 | Evicting a cache line with pending control request | Tony M. Brewer | 2024-06-18 |
| 11960768 | Memory-side cache directory-based request queue | Tony M. Brewer | 2024-04-16 |
| 11960403 | Variable execution time atomic operations | Tony M. Brewer | 2024-04-16 |
| 11953989 | Low-latency register error correction | Chris Baronne | 2024-04-09 |
| 11940919 | Recall pending cache line eviction | Tony M. Brewer | 2024-03-26 |
| 11914516 | Memory side cache request handling | Tony M. Brewer | 2024-02-27 |
| 11868300 | Deferred communications over a synchronous interface | Tony M. Brewer | 2024-01-09 |