Issued Patents 2024
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12182062 | Multi-tile memory management | Abhishek R. Appu, Altug Koker, Aravindh Anantaraman, Elmoustapha Ould-Ahmed-Vall, Valentin Andrei +14 more | 2024-12-31 |
| 12164952 | Barrier state save and restore for preemption in a graphics environment | Vasanth Ranganathan, Joydeep Ray, Abhishek R. Appu, Alan M. Curtis, Prathamesh Raghunath Shinde +3 more | 2024-12-10 |
| 12124852 | Instruction prefetch based on thread dispatch commands | Vasanth Ranganathan, Joydeep Ray, Pradeep Ramani | 2024-10-22 |
| 12099461 | Multi-tile memory management | Abhishek R. Appu, Altug Koker, Aravindh Anantaraman, Elmoustapha Ould-Ahmed-Vall, Valentin Andrei +14 more | 2024-09-24 |
| 12014183 | Base plus offset addressing for load/store messages | John Wiegert, Joydeep Ray, Timothy Bauer | 2024-06-18 |
| 11995737 | Thread scheduling over compute blocks for power optimization | Altug Koker, Balaji Vembu, Joydeep Ray, Abhishek R. Appu | 2024-05-28 |
| 11977895 | Hierarchical thread scheduling based on multiple barriers | Sabareesh Ganapathy, Fangwen Fu, Hong Jiang | 2024-05-07 |