Issued Patents 2024
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12020760 | ATPG testing method for latch based memories, for area reduction | Venkata Narayanan Srinivasan, Balwinder Singh Soni | 2024-06-25 |
| 11914499 | Systems and methods for preparing trace data | Thomas Szurmant, Misaele Marletti, Alessandro Daolio | 2024-02-27 |
| 11892505 | Debug and trace circuit in lockstep architectures, associated method, processing system, and apparatus | Anubhav Arora | 2024-02-06 |