Issued Patents 2024
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12164457 | Negotiating asymmetric link widths dynamically in a multi-lane link | — | 2024-12-10 |
| 12155474 | Characterizing and margining multi-voltage signal encoding for interconnects | Per E. Fornberg, Tal Israeli, Zuoguo Wu | 2024-11-26 |
| 12135581 | System, method, and apparatus for SRIS mode selection for PCIE | David J. Harriman, Daniel S. Froelich, Sean O. Stalley | 2024-11-05 |
| 12099458 | Pooled memory address translation | — | 2024-09-24 |
| 12056029 | In-system validation of interconnects by error injection and measurement | — | 2024-08-06 |
| 11934261 | Flit-based parallel-forward error correction and parity | — | 2024-03-19 |
| 11886312 | Characterizing error correlation based on error logging for computer buses | — | 2024-01-30 |
| 11860812 | Serdes link training | — | 2024-01-02 |