LS

Lakshminarayanan Striramassarma

IN Intel: 20 patents #38 of 4,430Top 1%
📍 Folsom, CA: #5 of 249 inventorsTop 3%
🗺 California: #411 of 67,048 inventorsTop 1%
Overall (2024): #2,398 of 561,600Top 1%
20
Patents 2024

Issued Patents 2024

Showing 1–20 of 20 patents

Patent #TitleCo-InventorsDate
12182035 Systems and methods for cache optimization Altug Koker, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall, Abhishek R. Appu, Aravindh Anantaraman +11 more 2024-12-31
12182062 Multi-tile memory management Abhishek R. Appu, Altug Koker, Aravindh Anantaraman, Elmoustapha Ould-Ahmed-Vall, Valentin Andrei +14 more 2024-12-31
12153541 Cache structure and utilization Altug Koker, Aravindh Anantaraman, Valentin Andrei, Abhishek R. Appu, Sean Coleman +9 more 2024-11-26
12141890 Enabling product SKUs based on chiplet configurations Altug Koker, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar +6 more 2024-11-12
12141094 Systolic disaggregation within a matrix accelerator architecture Prasoonkumar Surti, Subramaniam Maiyuran, Valentin Andrei, Abhishek R. Appu, Varghese George +6 more 2024-11-12
12124383 Systems and methods for cache optimization Altug Koker, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall, Abhishek R. Appu, Aravindh Anantaraman +11 more 2024-10-22
12112398 Disaggregation of system-on-chip (SOC) architecture Naveen Matam, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar +6 more 2024-10-08
12099461 Multi-tile memory management Abhishek R. Appu, Altug Koker, Aravindh Anantaraman, Elmoustapha Ould-Ahmed-Vall, Valentin Andrei +14 more 2024-09-24
12094048 Multi-tile graphics processor rendering Prasoonkumar Surti, Arthur Hunter, Kamal Sinha, Scott Janus, Brent Insko +1 more 2024-09-17
12066975 Cache structure and utilization Altug Koker, Aravindh Anantaraman, Valentin Andrei, Abhishek R. Appu, Sean Coleman +9 more 2024-08-20
12056789 Disaggregation of system-on-chip (SOC) architecture Naveen Matam, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar +6 more 2024-08-06
12056059 Systems and methods for cache optimization Altug Koker, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall, Abhishek R. Appu, Aravindh Anantaraman +11 more 2024-08-06
12032496 Efficient data sharing for graphics data processing operations Joydeep Ray, Altug Koker, Elmoustapha Ould-Ahmed-Vall, Michael Macpherson, Aravindh Anantaraman +4 more 2024-07-09
12013808 Multi-tile architecture for graphics operations Altug Koker, Ben J. Ashbaugh, Scott Janus, Aravindh Anantaraman, Abhishek R. Appu +11 more 2024-06-18
11995029 Multi-tile memory management for detecting cross tile access providing multi-tile inference scaling and providing page migration Prasoonkumar Surti, Varghese George, Ben J. Ashbaugh, Aravindh Anantaraman, Valentin Andrei +12 more 2024-05-28
11954062 Dynamic memory reconfiguration Joydeep Ray, Niranjan L. Cooray, Subramaniam Maiyuran, Altug Koker, Prasoonkumar Surti +11 more 2024-04-09
11934342 Assistance for hardware prefetch in cache access Altug Koker, Varghese George, Aravindh Anantaraman, Valentin Andrei, Abhishek R. Appu +11 more 2024-03-19
11908542 Energy efficient memory array with optimized burst read and write data access Charles Augustine, Somnath Paul, Turbo Majumder, Iqbal Rajwani, Andrew Lines +2 more 2024-02-20
11892950 Data prefetching for graphics data processing Vikranth Vemulapalli, Mike B. Macpherson, Aravindh Anantaraman, Ben J. Ashbaugh, Murali Ramadoss +16 more 2024-02-06
11868264 Sector cache for compression Abhishek R. Appu, Altug Koker, Joydeep Ray, David Puffer, Prasoonkumar Surti +4 more 2024-01-09