Issued Patents 2024
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12141081 | Training and operations with a double buffered memory topology | Chi-Ming Yeung, Yoshie Nakabayashi, Thomas J. Giovannini | 2024-11-12 |
| 11907139 | Memory system design using buffer(s) on a mother board | Chi-Ming Yeung, Yoshie Nakabayashi, Thomas J. Giovannini | 2024-02-20 |