Issued Patents 2024
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12111775 | Memory hub providing cache coherency protocol system method for multiple processor sockets comprising multiple XPUs | Matthew J. Adiletta, Hugh Wilkinson, Patrick Connor | 2024-10-08 |
| 12099408 | Memory striping approach that interleaves sub protected data words | Matthew J. Adiletta | 2024-09-24 |