Issued Patents 2024
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12176053 | Wordline system architecture supporting erase operation and I-V characterization | Ramesh Raghavan, Balaji Jayaraman | 2024-12-24 |
| 12087384 | Bias voltage generation circuit for memory devices | Bipul C. Paul, Nishtha Gaul, Shashank Nemawarkar | 2024-09-10 |