Issued Patents 2024
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12183822 | MOSFET structure with controllable channel length by forming lightly doped drains without using ion implantation | — | 2024-12-31 |
| 12159936 | Transistor structure and processing method therefore | — | 2024-12-03 |
| 12148500 | Method forming a semiconductor device structure having an underground interconnection embedded into a silicon substrate | Li-Ping Huang | 2024-11-19 |
| 12125910 | Transistor structure with increased gate dielectric thickness between gate-to-drain overlap region | Ming-Hong Kuo, Chun-Nan LU | 2024-10-22 |
| 12082400 | Memory cell structure with capacitor over transistor | — | 2024-09-03 |
| 12074205 | Transistor structure and related inverter | — | 2024-08-27 |
| 12068020 | Dynamic memory with sustainable storage architecture and clean up circuit | Chun Shiah, Bor-Doou Rong | 2024-08-20 |
| 11990548 | Transistor with low leakage currents and manufacturing method thereof | Weng-Dah Ken | 2024-05-21 |
| 11973120 | Miniaturized transistor structure with controlled dimensions of source/drain and contact-opening and related manufacture method | — | 2024-04-30 |
| 11972983 | Miniaturized transistor structure with controlled dimensions of source/drain and contact-opening and related manufacture method | — | 2024-04-30 |
| 11881481 | Complementary MOSFET structure with localized isolations in silicon substrate to reduce leakages and prevent latch-up | — | 2024-01-23 |
| 11877439 | Unified micro system with memory IC and logic IC | — | 2024-01-16 |
| 11869972 | Reduced-form-factor transistor with self-aligned terminals and adjustable on/off-currents and manufacture method thereof | — | 2024-01-09 |