JF

Jonathan R. Fales

CS Cadence Design Systems: 1 patents #31 of 141Top 25%
📍 South Burlington, VT: #33 of 77 inventorsTop 45%
🗺 Vermont: #147 of 407 inventorsTop 40%
Overall (2024): #409,379 of 561,600Top 75%
1
Patents 2024

Issued Patents 2024

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
11868698 Context-aware circuit design layout construct Joshua David Tygert, Rwik Sengupta, Timothy H. Pylant 2024-01-09