JP

Joel R. Phillips

CS Cadence Design Systems: 1 patents #31 of 141Top 25%
📍 San Jose, CA: #2,932 of 6,779 inventorsTop 45%
🗺 California: #26,178 of 67,048 inventorsTop 40%
Overall (2024): #403,831 of 561,600Top 75%
1
Patents 2024

Issued Patents 2024

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
12141233 Method, system, and computer program product for characterizing an electronic circuit using model order reduction-based envelope fourier techniques Marco Tony Lloyd Kassis, Mina Adel Aziz Farhan 2024-11-12