VK

Vikas Khandelwal

AL Astera Labs: 2 patents #8 of 13Top 65%
📍 San Jose, CA: #1,645 of 6,779 inventorsTop 25%
🗺 California: #13,937 of 67,048 inventorsTop 25%
Overall (2024): #106,390 of 561,600Top 20%
2
Patents 2024

Issued Patents 2024

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
12143288 Low-latency signaling-link retimer Casey Morrison, Enrique Musoll, Jitendra Mohan, Pulkit Khandelwal, Subbarao Arumilli +4 more 2024-11-12
11941436 Retimer with host-interactive data logging engine Ken (Keqin) Han, Casey Morrison, Charan Enugala, Pulkit Khandelwal 2024-03-26