Issued Patents 2022
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11526193 | Maintaining the correct time when counter values are transferred between clock domains | Harihara Subramanian Ranganathan | 2022-12-13 |
| 11502764 | FSYNC mismatch tracking | — | 2022-11-15 |
| 11502812 | Data protocol over clock line | — | 2022-11-15 |
| 11392166 | Clock skew detection and management | — | 2022-07-19 |
| 11290250 | Phase transport with frequency translation without a PLL | — | 2022-03-29 |