Issued Patents 2022
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11537531 | Cache memory that supports tagless addressing | Trung Diep | 2022-12-27 |
| 11513965 | Bandwidth boosted stacked memory | Krishna T. Malladi, Mu-Tien Chang, Dimin Niu | 2022-11-29 |
| 11500781 | Methods and apparatuses for addressing memory caches | Trung Diep | 2022-11-15 |
| 11487676 | Address mapping in memory systems | James Tringali | 2022-11-01 |
| 11475102 | Adaptive matrix multiplication accelerator for machine learning and deep learning applications | Dongyan Jiang, Dimin Niu | 2022-10-18 |
| 11436165 | High bandwidth memory system | Krishna T. Malladi, Dimin Niu | 2022-09-06 |
| 11437337 | Using electrical connections that traverse scribe lines to connect devices on a chip | Shuangchen Li, Wei Han, Dimin Niu, Yuhao Wang | 2022-09-06 |
| 11409684 | Processing accelerator architectures | Jilan LIN, Dimin Niu, Shuangchen Li, Yuan Xie | 2022-08-09 |
| 11409839 | Programmable and hierarchical control of execution of GEMM operation on accelerator | Yuhao Wang, Fei Sun, Fei Xue, Yen-Kuang Chen | 2022-08-09 |
| 11409672 | Unsuccessful write retry buffer | Brent Haukness | 2022-08-09 |
| 11397687 | Flash-integrated high bandwidth memory appliance | Krishna T. Malladi | 2022-07-26 |
| 11397698 | Asynchronous communication protocol compatible with synchronous DDR protocol | Dimin Niu, Mu-Tien Chang, Sun-Young Lim, Indong Kim, Jangseok Choi +1 more | 2022-07-26 |
| 11398453 | HBM silicon photonic TSV architecture for lookup computing AI accelerator | Peng Gu, Krishna T. Malladi | 2022-07-26 |
| 11392384 | Methods of breaking down coarse-grained tasks for fine-grained task re-scheduling | Fei Xue, Yuhao Wang, Fei Sun | 2022-07-19 |
| 11360906 | Inter-device processing system with cache coherency | Lide Duan, Hongyu Liu, Yen-Kuang Chen | 2022-06-14 |
| 11360766 | System and method for processing large datasets | Fei Xue, Shuangchen Li, Feng Zhu | 2022-06-14 |
| 11355163 | Memory interconnection architecture systems and methods | Wei Han, Shuangchen Li, Lide Duan, Dimin Niu, Yuhao Wang +1 more | 2022-06-07 |
| 11347665 | Memory module threading with staggered data transfers | Frederick A. Ware | 2022-05-31 |
| 11334284 | Database offloading engine | Andrew Chang, Jongmin Gim | 2022-05-17 |
| 11294571 | Coordinated in-module RAS features for synchronous DDR compatible memory | Mu-Tien Chang, Dimin Niu, Sun-Young Lim, Indong Kim, Jangseok Choi | 2022-04-05 |
| 11269811 | Method and apparatus for maximized dedupable memory | Dongyan Jiang, Qiang Peng | 2022-03-08 |
| 11263131 | System and method for allocating memory space | Shuangchen Li, Dimin Niu, Fei Sun, Jingjun Chu, Guoyang CHEN +3 more | 2022-03-01 |
| 11262980 | Computing accelerator using a lookup table | Krishna T. Malladi, Peng Gu, Robert Brennan | 2022-03-01 |
| 11244718 | Control of NAND flash memory for al applications | Fei Xue, Dimin Niu, Shuangchen Li | 2022-02-08 |
| 11226914 | Heterogeneous accelerator for highly efficient learning systems | Krishna T. Malladi | 2022-01-18 |