Issued Patents 2022
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11528033 | Neural network processor using compression and decompression of activation data to reduce memory bandwidth utilization | Joseph L. Corkery, Benjamin Eliot LUNDELL, Larry Marvin Wall, Chad B. McBride, Amol Ashok Ambardekar +2 more | 2022-12-13 |
| 11507349 | Neural processing element with single instruction multiple data (SIMD) compute lanes | Chad B. McBride, Amol Ashok Ambardekar, Boris Bobrov, Kent D. Cedola, Larry Marvin Wall | 2022-11-22 |
| 11494237 | Managing workloads of a deep neural network processor | Chad B. McBride, Amol Ashok Ambardekar, Boris Bobrov, Kent D. Cedola, Larry Marvin Wall | 2022-11-08 |
| 11487342 | Reducing power consumption in a neural network environment using data management | Amol Ashok Ambardekar, Chad B. McBride, Kent D. Cedola, Larry Marvin Wall | 2022-11-01 |
| 11476869 | Dynamically partitioning workload in a deep neural network module to reduce power consumption | Amol Ashok Ambardekar, Boris Bobrov, Chad B. McBride, Kent D. Cedola, Larry Marvin Wall | 2022-10-18 |
| 11405051 | Enhancing processing performance of artificial intelligence/machine hardware by data sharing and distribution as well as reuse of data in neuron buffer/line buffer | Chad B. McBride, Amol Ashok Ambardekar, Kent D. Cedola, Boris Bobrov, Larry Marvin Wall | 2022-08-02 |
| 11341399 | Reducing power consumption in a neural network processor by skipping processing operations | Amol Ashok Ambardekar, Chad B. McBride, Larry Marvin Wall, Kent D. Cedola, Boris Bobrov | 2022-05-24 |
| 11256976 | Dynamic sequencing of data partitions for optimizing memory utilization and performance of neural networks | Kent D. Cedola, Larry Marvin Wall, Boris Bobrov, Chad B. McBride, Amol Ashok Ambardekar | 2022-02-22 |