Issued Patents 2022
Showing 25 most recent of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11533077 | Pseudo-differential signaling for modified single-ended interface | Carl W. Werner | 2022-12-20 |
| 11507280 | Maintenance operations in a DRAM | Robert E. Palmer, John W. Poulton | 2022-11-22 |
| 11502681 | Method and system for balancing power-supply loading | Talip Ucar | 2022-11-15 |
| 11487679 | Semiconductor memory systems with on-die data buffering | Amir Amirkhany, Suresh Rajan, Mohammad Hekmat, Dinesh Patil | 2022-11-01 |
| 11487617 | Memory component with error-detect-correct code interface | Brent Haukness, Lawrence Lai | 2022-11-01 |
| 11481192 | Dual-domain combinational logic circuitry | John Eric Linstadt | 2022-10-25 |
| 11474959 | Memory module with reduced read/write turnaround overhead | Craig E. Hampel | 2022-10-18 |
| 11474957 | Memory access during memory calibration | Ian Shaeffer | 2022-10-18 |
| 11474590 | Dynamically changing data access bandwidth by selectively enabling and disabling data links | — | 2022-10-18 |
| 11468925 | DRAM interface mode with improved channel integrity and efficiency at high signaling rates | — | 2022-10-11 |
| 11467986 | Memory controller for selective rank or subrank access | Craig E. Hampel | 2022-10-11 |
| 11456025 | Hybrid memory module | John Eric Linstadt, Kenneth L. Wright | 2022-09-27 |
| 11455368 | MAC processing pipeline having conversion circuitry, and methods of operating same | Cheng C. Wang | 2022-09-27 |
| 11451218 | Data transmission using delayed timing signals | Ely Tsern, Brian S. Leibowitz, Jared L. Zerbe | 2022-09-20 |
| 11450356 | Synchronous signaling interface with over-clocked timing reference | John Eric Linstadt, Carl W. Werner | 2022-09-20 |
| 11442881 | MAC processing pipelines, circuitry to control and configure same, and methods of operating same | Cheng C. Wang | 2022-09-13 |
| 11403030 | Memory component with input/output data rate alignment | John Eric Linstadt, Torsten Partsch | 2022-08-02 |
| 11405174 | Signaling system with adaptive timing calibration | Bret G. Stott, Craig E. Hampel | 2022-08-02 |
| 11393550 | Memory system with error detection | John Eric Linstadt | 2022-07-19 |
| 11392452 | Serializing and deserializing stage testing | Angus William McLaren, Robert A. Heaton, Aaron Ali | 2022-07-19 |
| 11385959 | Memory repair method and apparatus based on error code tracking | Ely Tsern | 2022-07-12 |
| 11379136 | Adjustable access energy and access latency memory system and devices | John Eric Linstadt | 2022-07-05 |
| 11379392 | Multi-mode memory module and memory component | John Eric Linstadt, Kenneth L. Wright | 2022-07-05 |
| 11361839 | Command/address channel error detection | John Eric Linstadt | 2022-06-14 |
| 11347608 | Memory module with dedicated repair devices | Brent Haukness, John Eric Linstadt, Scott C. Best | 2022-05-31 |