Issued Patents 2022
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11513958 | Shared mid-level data cache | — | 2022-11-29 |
| 11507379 | Managing load and store instructions for memory barrier handling | Michael Bertone, David A. Carlson | 2022-11-22 |
| 11500779 | Vector prefetching for computing systems | — | 2022-11-15 |
| 11487874 | Prime and probe attack mitigation | — | 2022-11-01 |
| 11379368 | External way allocation circuitry for processor cores | Thomas F. Hummel | 2022-07-05 |
| 11379372 | Managing prefetch lookahead distance based on memory access latency | — | 2022-07-05 |
| 11379379 | Differential cache block sizing for computing systems | David Asher, Thomas F. Hummel | 2022-07-05 |
| 11372647 | Pipelines for secure multithread execution | — | 2022-06-28 |
| 11327759 | Managing low-level instructions and core interactions in multi-core processors | David A. Carlson, Michael Bertone, David Asher, Daniel Dever, Bradley Dobbie +1 more | 2022-05-10 |
| 11327890 | Partitioning in a processor cache | — | 2022-05-10 |
| 11307857 | Dynamic designation of instructions as sensitive for constraining multithreaded execution | — | 2022-04-19 |
| 11269644 | System and method for implementing strong load ordering in a processor using a circular ordering ring | David A. Carlson, Wilson P. Snyder, II | 2022-03-08 |
| 11263015 | Microarchitectural sensitive tag flow | — | 2022-03-01 |
| 11263043 | Managing processor core synchronization using interrupts | — | 2022-03-01 |