Issued Patents 2021
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11189627 | Method to reduce kink effect in semiconductor devices | Chieh-Fei Chiu, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu, Yong-Shiuan Tsair +1 more | 2021-11-30 |
| 11158377 | Device-region layout for embedded flash | Shih Kuang Yang, Ping-Cheng Li, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu +2 more | 2021-10-26 |
| 11133188 | Non-volatile memory semiconductor device with electrostatic discharge protection, planarization layers, and manufacturing method thereof | Yu-Ling Hsu, Chieh-Fei Chiu, Po-Wei Liu, Wen-Tuo Huang, Yong-Shiuan Tsair +1 more | 2021-09-28 |
| 11127827 | Control gate strap layout to improve a word line etch process window | Yu-Ling Hsu, Ping-Cheng Li, Po-Wei Liu, Wen-Tuo Huang, Yong-Shiuan Tsair +2 more | 2021-09-21 |
| 11101168 | Profile of deep trench isolation structure for isolation of high-voltage devices | — | 2021-08-24 |
| 11069695 | Floating gate test structure for embedded memory device | Yong-Shiuan Tsair | 2021-07-20 |
| 11031303 | Deep trench isolation structure and method of making the same | Tsung-Yu Yang, Yun-Chi Wu, Po-Wei Liu | 2021-06-08 |
| 11004858 | Semiconductor device and manufacturing method thereof | Tsun-Kai Tsao, Po-Wei Liu, Shun-Shing Yang, Wen-Tuo Huang, Yong-Shiuan Tsair +1 more | 2021-05-11 |
| 10978463 | Semiconductor device and manufacturing method thereof | ShihKuang Yang, Yong-Shiuan Tsair, Po-Wei Liu, Yu-Ling Hsu, Chieh-Fei Chiu +1 more | 2021-04-13 |
| 10943913 | Strap-cell architecture for embedded memory | Wen-Tuo Huang, Ping-Cheng Li, Po-Wei Liu, Yu-Ling Hsu, Yong-Shiuan Tsair +2 more | 2021-03-09 |