Issued Patents 2021
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11188234 | Cache line data | Cagdas Dirik | 2021-11-30 |
| 11182090 | Systems, devices, and methods for data migration | Paul Rosenfeld, Patrick A. La Fratta | 2021-11-23 |
| 11175859 | Managing memory commands in a memory subsystem by adjusting a maximum number of low priority commands in a DRAM controller | Patrick A. La Fratta, Laurent Isenegger | 2021-11-16 |
| 11169920 | Cache operations in a hybrid dual in-line memory module | Paul Stonelake, Horia Simionescu, Samir Mittal, Anirban Ray, Gurpreet Anand | 2021-11-09 |
| 11163486 | Memory sub-system-bounded memory function | Dhawal Bavishi | 2021-11-02 |
| 11163473 | Systems, devices, techniques, and methods for data migration | Paul Rosenfeld, Patrick A. La Fratta | 2021-11-02 |
| 11144240 | Memory sub-system for increasing bandwidth for command scheduling | Patrick A. La Fratta | 2021-10-12 |
| 11119908 | Systems and methods for memory system management | David A. Roberts | 2021-09-14 |
| 11016885 | Memory sub-system for decoding non-power-of-two addressable unit address boundaries | Patrick A. La Fratta, Chandrasekhar Nagarajan | 2021-05-25 |
| 11003602 | Memory protocol with command priority | — | 2021-05-11 |
| 10996890 | Memory module interfaces | — | 2021-05-04 |
| 10990321 | Memory sub-system for supporting deterministic and non-deterministic commands based on command expiration and the state of the intermediate command queue | Patrick A. La Fratta | 2021-04-27 |
| 10970222 | Eviction of a cache line based on a modification of a sector of the cache line | Dhawal Bavishi | 2021-04-06 |
| 10970247 | Conditional operation in an internal processor of a memory device | — | 2021-04-06 |
| 10963164 | Non-deterministic memory protocol | James A. Hall, Jr., Frank F. Ross | 2021-03-30 |
| 10908823 | Data transfer for wear leveling with bank clusters | — | 2021-02-02 |