Issued Patents 2021
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11055241 | Integrated circuit having lanes interchangeable between clock and data lanes in clock forward interface receiver | Ching-Hsiang Chang | 2021-07-06 |
| 11012087 | Encoding and decoding architecture for high speed data communication system and related physical layer circuit, transmitter and receiver and communication system thereof | Ching-Hsiang Chang | 2021-05-18 |