Issued Patents 2021
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11176301 | Noise impact on function (NIOF) reduction for integrated circuit design | Jose L. Neves | 2021-11-16 |
| 11030376 | Net routing for integrated circuit (IC) design | Jose L. Neves | 2021-06-08 |
| 10943040 | Clock gating latch placement | Jesse Peter Surprise, Gerald Strevig, III, Shawn Kollesar | 2021-03-09 |
| 10885243 | Logic partition reporting for integrated circuit design | Jose L. Neves | 2021-01-05 |