Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
CJ

Chia-Hong Jan

Intel: 12 patents #123 of 5,160Top 3%
Portland, OR: #63 of 1,855 inventorsTop 4%
Oregon: #104 of 4,388 inventorsTop 3%
Overall (2021): #5,931 of 548,734Top 2%
12 Patents 2021

Issued Patents 2021

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDate
11205708 Dual self-aligned gate endcap (SAGE) architectures Sairam Subramanian, Walid M. Hafez, Sridhar Govindaraju, Mark Liu, Szuya S. Liao +2 more 2021-12-21
11139370 Dielectric and isolation lower fin material for fin-based electronics Walid M. Hafez 2021-10-05
11121040 Multi voltage threshold transistors through process and design-induced multiple work functions Chen-Guan Lee, Everett S. Cassidy-Comfort, Joodong Park, Walid M. Hafez, Rahul Ramaswamy +2 more 2021-09-14
11114538 Transistor with an airgap spacer adjacent to a transistor gate Chen-Guan Lee, Joodong Park, En-Shao Liu, Everett S. Cassidy-Comfort, Walid M. Hafez 2021-09-07
11075286 Hybrid finfet structure with bulk source/drain regions Walid M. Hafez, Neville L. Dias, Rahul Ramaswamy, Hsu-Yu Chang, Roman W. Olac-Vaw +1 more 2021-07-27
10964690 Resistor between gates in self-aligned gate edge architecture Roman W. Olac-Vaw, Walid M. Hafez, Hsu-Yu Chang, Neville L. Dias, Rahul Ramaswamy +2 more 2021-03-30
10950606 Dual fin endcap for self-aligned gate edge (SAGE) architectures Walid M. Hafez, Roman W. Olac-Vaw 2021-03-16
10930729 Fin-based thin film resistor Walid M. Hafez, Neville L. Dias, Rahul Ramaswamy, Hsu-Yu Chang, Roman W. Olac-Vaw +1 more 2021-02-23
10923574 Transistor with inner-gate spacer En-Shao Liu, Joodong Park, Chen-Guan Lee, Jui-Yen Lin 2021-02-16
10903372 Metal-oxide-polysilicon tunable resistor for flexible circuit design and method of fabricating same Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi 2021-01-26
10892192 Non-planar I/O and logic semiconductor devices having different workfunction on common substrate Roman W. Olac-Vaw, Walid M. Hafez, Pei-Chi Liu 2021-01-12
10892261 Metal resistor and self-aligned gate edge (SAGE) architecture having a metal resistor Walid M. Hafez, Roman W. Olac-Vaw, Joodong Park, Chen-Guan Lee 2021-01-12