Issued Patents 2021
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11196953 | Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Daniel Frederic Finchelstein, David Patterson, William R. Mark, Jason Redgrave, Ofer Shacham | 2021-12-07 |
| 11190718 | Line buffer unit for image processor | Neeti Desai, Qiuling Zhu, Jason Redgrave, Ofer Shacham, Daniel Frederic Finchelstein | 2021-11-30 |
| 11182138 | Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure | — | 2021-11-23 |
| 11153464 | Two dimensional shift array for image processor | Ofer Shacham, Jason Redgrave, Qiuling Zhu, Daniel Frederic Finchelstein, David Patterson +1 more | 2021-10-19 |
| 11138013 | Energy efficient processor core architecture for image processor | Jason Redgrave, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu | 2021-10-05 |
| 11140293 | Sheet generator for image processor | Jason Redgrave, Ofer Shacham, Qiuling Zhu, Daniel Frederic Finchelstein | 2021-10-05 |
| 11030005 | Configuration of application software on multi-core image processor | Hyunchul Park | 2021-06-08 |
| 10996988 | Program code transformations to improve image processor runtime efficiency | Hyunchul Park | 2021-05-04 |
| 10915319 | Two dimensional masked shift instruction | — | 2021-02-09 |
| 10915773 | Statistics operations on two dimensional image processor | Edward Chang, Daniel Frederic Finchelstein, Szepo Robert Hung, Ofer Shacham | 2021-02-09 |
| 10884959 | Way partitioning for a system-level cache | Vinod Chamarty, Xiaoyu Ma, Hongil Yoon, Keith Robert Pflederer, Weiping Liao +5 more | 2021-01-05 |