Issued Patents 2021
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11139209 | 3D circuit provided with mesa isolation for the ground plane zone | Perrine Batude | 2021-10-05 |
| 11024544 | Assembly for 3D circuit with superposed transistor levels | Lamine Benaissa, Laurent Brunet | 2021-06-01 |
| 11011425 | Production of a 3D circuit with upper level transistor provided with a gate dielectric derived from a substrate transfer | Perrine Batude, Maud Vinet | 2021-05-18 |